/*
 * (C) Copyright 2007-2015
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Jerry Wang <wangflord@allwinnertech.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef   _MCTL_REG_H
#define   _MCTL_REG_H

#define MCTL_COM_BASE		0x01c62000
#define MCTL_CTL_BASE		0x01c63000
#define MCTL_PHY_BASE		0x01c65000
#define MCTL_RAM_BASE		0x01c64000

#define MCTL_CTL0_BASE		0x01c63000
#define MCTL_CTL1_BASE		0x01c64000
#define MCTL_PHY0_BASE		0x01c65000
#define MCTL_PHY1_BASE		0x01c66000


//#define MCTL_CTL0			0x01c63000
//#define MCTL_CTL1			0x01c64000
//#define MCTL_PHY0			0x01c65000
//#define MCTL_PHY1			0x01c66000

#define SDR_COM_CR				(MCTL_COM_BASE + 0x00)
#define SDR_COM_CCR				(MCTL_COM_BASE + 0x04)
#define SDR_COM_DBGCR			(MCTL_COM_BASE + 0x08)
#define SDR_COM_DBGCR1			(MCTL_COM_BASE + 0x0c)
#define SDR_COM_RMCR			(MCTL_COM_BASE + 0x10)
#define SDR_COM_MMCR			(MCTL_COM_BASE + 0x30)
#define SDR_COM_MBAGCR			(MCTL_COM_BASE + 0x70)
#define SDR_COM_MBACR			(MCTL_COM_BASE + 0x74)
#define SDR_COM_MAER			(MCTL_COM_BASE + 0x88)
#define SDR_COM_MDFSCR			(MCTL_COM_BASE + 0x100)
#define SDR_COM_MDFSMER			(MCTL_COM_BASE + 0x104)
#define SDR_COM_MDFSMRMR		(MCTL_COM_BASE + 0x108)
#define SDR_COM_MDFSTR0			(MCTL_COM_BASE + 0x10c)
#define SDR_COM_MDFSTR1			(MCTL_COM_BASE + 0x110)
#define SDR_COM_MDFSTR2			(MCTL_COM_BASE + 0x114)
#define SDR_COM_MDFSTR3			(MCTL_COM_BASE + 0x118)
#define SDR_COM_MDFSGCR			(MCTL_COM_BASE + 0x11c)
#define SDR_COM_MDFSIVR			(MCTL_COM_BASE + 0x13c)
#define SDR_COM_MDFSTCR			(MCTL_COM_BASE + 0x14c)

#define MC_CR					(MCTL_COM_BASE + 0x00)
#define MC_CCR					(MCTL_COM_BASE + 0x04)
#define MC_DBGCR				(MCTL_COM_BASE + 0x08)
#define MC_DBGCR1				(MCTL_COM_BASE + 0x0c)
#define MC_RMCR					(MCTL_COM_BASE + 0x10)
#define MC_MMCR					(MCTL_COM_BASE + 0x30)
#define MC_MBAGCR				(MCTL_COM_BASE + 0x70)
#define MC_MBACR				(MCTL_COM_BASE + 0x74)
#define MC_MAER					(MCTL_COM_BASE + 0x88)
#define MC_MDFSCR				(MCTL_COM_BASE + 0x100)
#define MC_MDFSMER				(MCTL_COM_BASE + 0x104)
#define MC_MDFSMRMR				(MCTL_COM_BASE + 0x108)
#define MC_MDFSTR0				(MCTL_COM_BASE + 0x10c)
#define MC_MDFSTR1				(MCTL_COM_BASE + 0x110)
#define MC_MDFSTR2				(MCTL_COM_BASE + 0x114)
#define MC_MDFSTR3				(MCTL_COM_BASE + 0x118)
#define MC_MDFSGCR				(MCTL_COM_BASE + 0x11c)
#define MC_MDFSIVR				(MCTL_COM_BASE + 0x13c)
#define MC_MDFSTCR				(MCTL_COM_BASE + 0x14c)

#define SDR_SCTL				(MCTL_CTL_BASE + 0x04)
#define SDR_SSTAT				(MCTL_CTL_BASE + 0x08)
#define SDR_MCMD				(MCTL_CTL_BASE + 0x40)
#define SDR_CMDSTAT				(MCTL_CTL_BASE + 0x4c)
#define SDR_CMDSTATEN			(MCTL_CTL_BASE + 0x50)
#define SDR_MRRCFG0				(MCTL_CTL_BASE + 0x60)
#define SDR_MRRSTAT0			(MCTL_CTL_BASE + 0x64)
#define SDR_MRRSTAT1			(MCTL_CTL_BASE + 0x68)
#define SDR_MCFG1				(MCTL_CTL_BASE + 0x7c)
#define SDR_MCFG				(MCTL_CTL_BASE + 0x80)
#define SDR_PPCFG				(MCTL_CTL_BASE + 0x84)
#define SDR_MSTAT				(MCTL_CTL_BASE + 0x88)
#define SDR_LP2ZQCFG			(MCTL_CTL_BASE + 0x8c)
#define SDR_DTUSTAT				(MCTL_CTL_BASE + 0x94)
#define SDR_DTUNA				(MCTL_CTL_BASE + 0x98)
#define SDR_DTUNE				(MCTL_CTL_BASE + 0x9c)
#define SDR_DTUPRD0				(MCTL_CTL_BASE + 0xa0)
#define SDR_DTUPRD1				(MCTL_CTL_BASE + 0xa4)
#define SDR_DTUPRD2				(MCTL_CTL_BASE + 0xa8)
#define SDR_DTUPRD3				(MCTL_CTL_BASE + 0xac)
#define SDR_DTUAWDT				(MCTL_CTL_BASE + 0xb0)
#define SDR_TOGCNT1U			(MCTL_CTL_BASE + 0xc0)
#define SDR_TOGCNT100N			(MCTL_CTL_BASE + 0xcc)
#define SDR_TREFI				(MCTL_CTL_BASE + 0xd0)
#define SDR_TMRD				(MCTL_CTL_BASE + 0xd4)
#define SDR_TRFC				(MCTL_CTL_BASE + 0xd8)
#define SDR_TRP					(MCTL_CTL_BASE + 0xdc)
#define SDR_TRTW				(MCTL_CTL_BASE + 0xe0)
#define SDR_TAL					(MCTL_CTL_BASE + 0xe4)
#define SDR_TCL					(MCTL_CTL_BASE + 0xe8)
#define SDR_TCWL				(MCTL_CTL_BASE + 0xec)
#define SDR_TRAS				(MCTL_CTL_BASE + 0xf0)
#define SDR_TRC					(MCTL_CTL_BASE + 0xf4)
#define SDR_TRCD				(MCTL_CTL_BASE + 0xf8)
#define SDR_TRRD				(MCTL_CTL_BASE + 0xfc)
#define SDR_TRTP				(MCTL_CTL_BASE + 0x100)
#define SDR_TWR					(MCTL_CTL_BASE + 0x104)
#define SDR_TWTR				(MCTL_CTL_BASE + 0x108)
#define SDR_TEXSR				(MCTL_CTL_BASE + 0x10c)
#define SDR_TXP					(MCTL_CTL_BASE + 0x110)
#define SDR_TXPDLL				(MCTL_CTL_BASE + 0x114)
#define SDR_TZQCS				(MCTL_CTL_BASE + 0x118)
#define SDR_TZQCSI				(MCTL_CTL_BASE + 0x11c)
#define SDR_TDQS  				(MCTL_CTL_BASE + 0x120)
#define SDR_TCKSRE 				(MCTL_CTL_BASE + 0x124)
#define SDR_TCKSRX 				(MCTL_CTL_BASE + 0x128)
#define SDR_TCKE 				(MCTL_CTL_BASE + 0x12c)
#define SDR_TMOD 				(MCTL_CTL_BASE + 0x130)
#define SDR_TRSTL 				(MCTL_CTL_BASE + 0x134)
#define SDR_TZQCL 				(MCTL_CTL_BASE + 0x138)
#define SDR_TMRR 				(MCTL_CTL_BASE + 0x13c)
#define SDR_TCKESR 				(MCTL_CTL_BASE + 0x140)
#define SDR_TDPD 				(MCTL_CTL_BASE + 0x144)
#define SDR_DTUWACTL			(MCTL_CTL_BASE + 0x200)
#define SDR_DTURACTL			(MCTL_CTL_BASE + 0x204)
#define SDR_DTUCFG				(MCTL_CTL_BASE + 0x208)
#define SDR_DTUECTL				(MCTL_CTL_BASE + 0x20c)
#define SDR_DTUWD0				(MCTL_CTL_BASE + 0x210)
#define SDR_DTUWD1				(MCTL_CTL_BASE + 0x214)
#define SDR_DTUWD2				(MCTL_CTL_BASE + 0x218)
#define SDR_DTUWD3				(MCTL_CTL_BASE + 0x21c)
#define SDR_DTUWDM				(MCTL_CTL_BASE + 0x220)
#define SDR_DTURD0				(MCTL_CTL_BASE + 0x224)
#define SDR_DTURD1				(MCTL_CTL_BASE + 0x224)
#define SDR_DTURD2				(MCTL_CTL_BASE + 0x22c)
#define SDR_DTURD3				(MCTL_CTL_BASE + 0x230)
#define SDR_DTULFSRWD 		    (MCTL_CTL_BASE + 0x234)
#define SDR_DTULFSRRD 		    (MCTL_CTL_BASE + 0x238)
#define SDR_DTUEAF	 		    (MCTL_CTL_BASE + 0x23c)
#define SDR_DFITCTLDLY 		    (MCTL_CTL_BASE + 0x240)
#define SDR_DFIODTCFG 		    (MCTL_CTL_BASE + 0x244)
#define SDR_DFIODTCFG1 		    (MCTL_CTL_BASE + 0x248)
#define SDR_DFIODTRMAP 		    (MCTL_CTL_BASE + 0x24c)
#define SDR_DFITPHYWRD 		    (MCTL_CTL_BASE + 0x250)
#define SDR_DFITPHYWRL 		    (MCTL_CTL_BASE + 0x254)
#define SDR_DFITRDDEN 		    (MCTL_CTL_BASE + 0x260)
#define SDR_DFITPHYRDL 		    (MCTL_CTL_BASE + 0x264)
#define SDR_DFITPHYUPDTYPE0	    (MCTL_CTL_BASE + 0x270)
#define SDR_DFITPHYUPDTYPE1	    (MCTL_CTL_BASE + 0x274)
#define SDR_DFITPHYUPDTYPE2	    (MCTL_CTL_BASE + 0x278)
#define SDR_DFITPHYUPDTYPE3	    (MCTL_CTL_BASE + 0x27c)

#define Mx_MSTR           		(MCTL_CTL_BASE + 0x00000000)
#define Mx_STATR          		(MCTL_CTL_BASE + 0x00000004)
#define Mx_MRCTRL0        		(MCTL_CTL_BASE + 0x00000010)
#define Mx_MRCTRL1        		(MCTL_CTL_BASE + 0x00000014)
#define Mx_MRSTATR        		(MCTL_CTL_BASE + 0x00000018)
#define Mx_DERATEEN       		(MCTL_CTL_BASE + 0x00000020)
#define Mx_DERATEINT      		(MCTL_CTL_BASE + 0x00000024)
#define Mx_PWRCTL         		(MCTL_CTL_BASE + 0x00000030)
#define Mx_PWRTMG         		(MCTL_CTL_BASE + 0x00000034)
#define Mx_RFSHCTL0       		(MCTL_CTL_BASE + 0x00000050)
#define Mx_RFSHCTL1       		(MCTL_CTL_BASE + 0x00000054)
#define Mx_RFSHCTL3       		(MCTL_CTL_BASE + 0x00000060)
#define Mx_RFSHTMG        		(MCTL_CTL_BASE + 0x00000064)
#define Mx_INT0           		(MCTL_CTL_BASE + 0x000000d0)
#define Mx_INT1           		(MCTL_CTL_BASE + 0x000000d4)
#define Mx_INT2           		(MCTL_CTL_BASE + 0x000000d8)
#define Mx_INT3           		(MCTL_CTL_BASE + 0x000000dc)
#define Mx_INT4           		(MCTL_CTL_BASE + 0x000000e0)
#define Mx_INT5           		(MCTL_CTL_BASE + 0x000000e4)
#define Mx_RANKCTL        		(MCTL_CTL_BASE + 0x000000f4)
#define Mx_DRAMTMG0       		(MCTL_CTL_BASE + 0x00000100)
#define Mx_DRAMTMG1       		(MCTL_CTL_BASE + 0x00000104)
#define Mx_DRAMTMG2       		(MCTL_CTL_BASE + 0x00000108)
#define Mx_DRAMTMG3       		(MCTL_CTL_BASE + 0x0000010C)
#define Mx_DRAMTMG4       		(MCTL_CTL_BASE + 0x00000110)
#define Mx_DRAMTMG5       		(MCTL_CTL_BASE + 0x00000114)
#define Mx_DRAMTMG6       		(MCTL_CTL_BASE + 0x00000118)
#define Mx_DRAMTMG7       		(MCTL_CTL_BASE + 0x0000011c)
#define Mx_DRAMTMG8       		(MCTL_CTL_BASE + 0x00000120)
#define Mx_ZQCTRL0        		(MCTL_CTL_BASE + 0x00000180)
#define Mx_ZQCTRL1        		(MCTL_CTL_BASE + 0x00000184)
#define Mx_ZQCTRL2        		(MCTL_CTL_BASE + 0x00000188)
#define Mx_ZQSTAT         		(MCTL_CTL_BASE + 0x0000018c)
#define Mx_PITMG0         		(MCTL_CTL_BASE + 0x00000190)
#define Mx_PITMG1         		(MCTL_CTL_BASE + 0x00000194)
#define Mx_PLPCFG0        		(MCTL_CTL_BASE + 0x00000198)
#define Mx_UPD0           		(MCTL_CTL_BASE + 0x000001A0)
#define Mx_UPD1           		(MCTL_CTL_BASE + 0x000001A4)
#define Mx_UPD2           		(MCTL_CTL_BASE + 0x000001A8)
#define Mx_UPD3           		(MCTL_CTL_BASE + 0x000001AC)
#define Mx_PIMISC         		(MCTL_CTL_BASE + 0x000001B0)
#define Mx_TRAINCTL0      		(MCTL_CTL_BASE + 0x000001D0)
#define Mx_TRAINCTL1      		(MCTL_CTL_BASE + 0x000001D4)
#define Mx_TRAINCTL2      		(MCTL_CTL_BASE + 0x000001D8)
#define Mx_TRAINSTAT      		(MCTL_CTL_BASE + 0x000001DC)
#define Mx_ADDRMAP0       		(MCTL_CTL_BASE + 0x00000200)
#define Mx_ADDRMAP1       		(MCTL_CTL_BASE + 0x00000204)
#define Mx_ADDRMAP2       		(MCTL_CTL_BASE + 0x00000208)
#define Mx_ADDRMAP3       		(MCTL_CTL_BASE + 0x0000020C)
#define Mx_ADDRMAP4       		(MCTL_CTL_BASE + 0x00000210)
#define Mx_ADDRMAP5       		(MCTL_CTL_BASE + 0x00000214)
#define Mx_ADDRMAP6       		(MCTL_CTL_BASE + 0x00000218)
#define Mx_ODTCFG         		(MCTL_CTL_BASE + 0x00000240)
#define Mx_ODTMAP         		(MCTL_CTL_BASE + 0x00000244)
#define Mx_SCHED          		(MCTL_CTL_BASE + 0x00000250)

#define M0_MSTR           		(MCTL_CTL_BASE + 0x000)
#define M0_STATR          		(MCTL_CTL_BASE + 0x004)
#define M0_MRCTRL0        		(MCTL_CTL_BASE + 0x010)
#define M0_MRCTRL1        		(MCTL_CTL_BASE + 0x014)
#define M0_MRSTATR        		(MCTL_CTL_BASE + 0x018)
#define M0_DERATEEN       		(MCTL_CTL_BASE + 0x020)
#define M0_DERATEINT      		(MCTL_CTL_BASE + 0x024)
#define M0_PWRCTL         		(MCTL_CTL_BASE + 0x030)
#define M0_PWRTMG         		(MCTL_CTL_BASE + 0x034)
#define M0_RFSHCTL0       		(MCTL_CTL_BASE + 0x050)
#define M0_RFSHCTL1       		(MCTL_CTL_BASE + 0x054)
#define M0_RFSHCTL3       		(MCTL_CTL_BASE + 0x060)
#define M0_RFSHTMG        		(MCTL_CTL_BASE + 0x064)
#define M0_INT0           		(MCTL_CTL_BASE + 0x0d0)
#define M0_INT1           		(MCTL_CTL_BASE + 0x0d4)
#define M0_INT2           		(MCTL_CTL_BASE + 0x0d8)
#define M0_INT3           		(MCTL_CTL_BASE + 0x0dc)
#define M0_INT4           		(MCTL_CTL_BASE + 0x0e0)
#define M0_INT5           		(MCTL_CTL_BASE + 0x0e4)
#define M0_RANKCTL        		(MCTL_CTL_BASE + 0x0f4)
#define M0_DRAMTMG0       		(MCTL_CTL_BASE + 0x100)
#define M0_DRAMTMG1       		(MCTL_CTL_BASE + 0x104)
#define M0_DRAMTMG2       		(MCTL_CTL_BASE + 0x108)
#define M0_DRAMTMG3       		(MCTL_CTL_BASE + 0x10C)
#define M0_DRAMTMG4       		(MCTL_CTL_BASE + 0x110)
#define M0_DRAMTMG5       		(MCTL_CTL_BASE + 0x114)
#define M0_DRAMTMG6       		(MCTL_CTL_BASE + 0x118)
#define M0_DRAMTMG7       		(MCTL_CTL_BASE + 0x11c)
#define M0_DRAMTMG8       		(MCTL_CTL_BASE + 0x120)
#define M0_ZQCTRL0        		(MCTL_CTL_BASE + 0x180)
#define M0_ZQCTRL1        		(MCTL_CTL_BASE + 0x184)
#define M0_ZQCTRL2        		(MCTL_CTL_BASE + 0x188)
#define M0_ZQSTAT         		(MCTL_CTL_BASE + 0x18c)
#define M0_PITMG0         		(MCTL_CTL_BASE + 0x190)
#define M0_PITMG1         		(MCTL_CTL_BASE + 0x194)
#define M0_PLPCFG0        		(MCTL_CTL_BASE + 0x198)
#define M0_UPD0           		(MCTL_CTL_BASE + 0x1A0)
#define M0_UPD1           		(MCTL_CTL_BASE + 0x1A4)
#define M0_UPD2           		(MCTL_CTL_BASE + 0x1A8)
#define M0_UPD3           		(MCTL_CTL_BASE + 0x1AC)
#define M0_PIMISC         		(MCTL_CTL_BASE + 0x1B0)
#define M0_TRAINCTL0      		(MCTL_CTL_BASE + 0x1D0)
#define M0_TRAINCTL1      		(MCTL_CTL_BASE + 0x1D4)
#define M0_TRAINCTL2      		(MCTL_CTL_BASE + 0x1D8)
#define M0_TRAINSTAT      		(MCTL_CTL_BASE + 0x1DC)
#define M0_ADDRMAP0       		(MCTL_CTL_BASE + 0x200)
#define M0_ADDRMAP1       		(MCTL_CTL_BASE + 0x204)
#define M0_ADDRMAP2       		(MCTL_CTL_BASE + 0x208)
#define M0_ADDRMAP3       		(MCTL_CTL_BASE + 0x20C)
#define M0_ADDRMAP4       		(MCTL_CTL_BASE + 0x210)
#define M0_ADDRMAP5       		(MCTL_CTL_BASE + 0x214)
#define M0_ADDRMAP6       		(MCTL_CTL_BASE + 0x218)
#define M0_ODTCFG         		(MCTL_CTL_BASE + 0x240)
#define M0_ODTMAP         		(MCTL_CTL_BASE + 0x244)
#define M0_SCHED          		(MCTL_CTL_BASE + 0x250)

#define M0_SCHED          		(MCTL_CTL_BASE + 0x250)
#define M0_PERFHPR0        		(MCTL_CTL_BASE + 0x258)
#define M0_PERFHPR1        		(MCTL_CTL_BASE + 0x25c)
#define M0_PERFLPR0        		(MCTL_CTL_BASE + 0x260)
#define M0_PERFLPR1        		(MCTL_CTL_BASE + 0x264)
#define M0_PERFWR0        		(MCTL_CTL_BASE + 0x268)
#define M0_PERFWR1        		(MCTL_CTL_BASE + 0x26c)

#define M0_DCMDAPC						(MCTL_CTL_BASE + 0x304)

#define P0_PIR                 	(MCTL_PHY_BASE + 0x004)
#define P0_PGCR0               	(MCTL_PHY_BASE + 0x008)
#define P0_PGCR1               	(MCTL_PHY_BASE + 0x00C)
#define P0_PGCR2               	(MCTL_PHY_BASE + 0x010)
#define P0_PGCR3               	(MCTL_PHY_BASE + 0x014)
#define P0_PGSR0               	(MCTL_PHY_BASE + 0x018)
#define P0_PGSR1               	(MCTL_PHY_BASE + 0x01C)
#define P0_PLLGCR              	(MCTL_PHY_BASE + 0x020)
#define P0_PTR0                	(MCTL_PHY_BASE + 0x024)
#define P0_PTR1                	(MCTL_PHY_BASE + 0x028)
#define P0_PTR2                	(MCTL_PHY_BASE + 0x02C)
#define P0_PTR3                	(MCTL_PHY_BASE + 0x030)
#define P0_PTR4                	(MCTL_PHY_BASE + 0x034)
#define P0_ACMDLR              	(MCTL_PHY_BASE + 0x038)
#define P0_ACLCDLR             	(MCTL_PHY_BASE + 0x03C)
#define P0_ACBDLR0             	(MCTL_PHY_BASE + 0x040)
#define P0_ACBDLR1             	(MCTL_PHY_BASE + 0x044)
#define P0_ACBDLR2             	(MCTL_PHY_BASE + 0x048)
#define P0_ACBDLR3             	(MCTL_PHY_BASE + 0x04C)
#define P0_ACBDLR4             	(MCTL_PHY_BASE + 0x050)
#define P0_ACBDLR5             	(MCTL_PHY_BASE + 0x054)
#define P0_ACBDLR6             	(MCTL_PHY_BASE + 0x058)
#define P0_ACBDLR7             	(MCTL_PHY_BASE + 0x05C)
#define P0_ACBDLR8             	(MCTL_PHY_BASE + 0x060)
#define P0_ACBDLR9             	(MCTL_PHY_BASE + 0x064)
#define P0_ACIOCR0             	(MCTL_PHY_BASE + 0x068)
#define P0_ACIOCR1             	(MCTL_PHY_BASE + 0x06C)
#define P0_ACIOCR2             	(MCTL_PHY_BASE + 0x070)
#define P0_ACIOCR3             	(MCTL_PHY_BASE + 0x074)
#define P0_ACIOCR4             	(MCTL_PHY_BASE + 0x078)
#define P0_ACIOCR5             	(MCTL_PHY_BASE + 0x07C)
#define P0_DXCCR               	(MCTL_PHY_BASE + 0x080)
#define P0_DSGCR               	(MCTL_PHY_BASE + 0x084)
#define P0_DCR                 	(MCTL_PHY_BASE + 0x088)
#define P0_DTPR0               	(MCTL_PHY_BASE + 0x08C)
#define P0_DTPR1               	(MCTL_PHY_BASE + 0x090)
#define P0_DTPR2               	(MCTL_PHY_BASE + 0x094)
#define P0_DTPR3               	(MCTL_PHY_BASE + 0x098)
#define P0_MR0                 	(MCTL_PHY_BASE + 0x09C)
#define P0_MR1                 	(MCTL_PHY_BASE + 0x0A0)
#define P0_MR2                 	(MCTL_PHY_BASE + 0x0A4)
#define P0_MR3                 	(MCTL_PHY_BASE + 0x0A8)
#define P0_ODTCR               	(MCTL_PHY_BASE + 0x0AC)
#define P0_DTCR                	(MCTL_PHY_BASE + 0x0B0)
#define P0_DTAR0               	(MCTL_PHY_BASE + 0x0B4)
#define P0_DTAR1               	(MCTL_PHY_BASE + 0x0B8)
#define P0_DTAR2               	(MCTL_PHY_BASE + 0x0BC)
#define P0_DTAR3               	(MCTL_PHY_BASE + 0x0C0)
#define P0_DTDR0               	(MCTL_PHY_BASE + 0x0C4)
#define P0_DTDR1               	(MCTL_PHY_BASE + 0x0C8)
#define P0_DTEDR0              	(MCTL_PHY_BASE + 0x0CC)
#define P0_DTEDR1              	(MCTL_PHY_BASE + 0x0D0)
#define P0_RDIMMGCR0           	(MCTL_PHY_BASE + 0x0D4)
#define P0_RDIMMGCR1           	(MCTL_PHY_BASE + 0x0D8)
#define P0_RDIMMCR0            	(MCTL_PHY_BASE + 0x0DC)
#define P0_RDIMMCR1            	(MCTL_PHY_BASE + 0x0E0)
#define P0_GPR0                	(MCTL_PHY_BASE + 0x0E4)
#define P0_GPR1                	(MCTL_PHY_BASE + 0x0E8)
#define P0_CATR0               	(MCTL_PHY_BASE + 0x0EC)
#define P0_CATR1               	(MCTL_PHY_BASE + 0x0F0)
#define P0_DQSDR               	(MCTL_PHY_BASE + 0x0F4)

#define P0_BISTRR              	(MCTL_PHY_BASE + 0x1C0)
#define P0_BISTWCR             	(MCTL_PHY_BASE + 0x1C4)
#define P0_BISTMSKR0           	(MCTL_PHY_BASE + 0x1C8)
#define P0_BISTMSKR1           	(MCTL_PHY_BASE + 0x1CC)
#define P0_BISTMSKR2           	(MCTL_PHY_BASE + 0x1D0)
#define P0_BISTLSR             	(MCTL_PHY_BASE + 0x1D4)
#define P0_BISTAR0             	(MCTL_PHY_BASE + 0x1D8)
#define P0_BISTAR1             	(MCTL_PHY_BASE + 0x1DC)
#define P0_BISTAR2             	(MCTL_PHY_BASE + 0x1E0)
#define P0_BISTUDPR            	(MCTL_PHY_BASE + 0x1E4)
#define P0_BISTGSR             	(MCTL_PHY_BASE + 0x1E8)
#define P0_BISTWER             	(MCTL_PHY_BASE + 0x1EC)
#define P0_BISTBER0            	(MCTL_PHY_BASE + 0x1F0)
#define P0_BISTBER1            	(MCTL_PHY_BASE + 0x1F4)
#define P0_BISTBER2            	(MCTL_PHY_BASE + 0x1F8)
#define P0_BISTBER3            	(MCTL_PHY_BASE + 0x1FC)
#define P0_BISTWCSR            	(MCTL_PHY_BASE + 0x200)
#define P0_BISTFWR0            	(MCTL_PHY_BASE + 0x204)
#define P0_BISTFWR1            	(MCTL_PHY_BASE + 0x208)
#define P0_BISTFWR2            	(MCTL_PHY_BASE + 0x20C)
#define P0_IOVCR0              	(MCTL_PHY_BASE + 0x238)
#define P0_IOVCR1              	(MCTL_PHY_BASE + 0x23C)
#define P0_ZQ0CR                (MCTL_PHY_BASE + 0x240)
#define P0_ZQ0PR               	(MCTL_PHY_BASE + 0x244)
#define P0_ZQ0DR               	(MCTL_PHY_BASE + 0x248)
#define P0_ZQ0SR               	(MCTL_PHY_BASE + 0x24C)
#define P0_ZQ1CR                (MCTL_PHY_BASE + 0x250)
#define P0_ZQ1PR               	(MCTL_PHY_BASE + 0x254)
#define P0_ZQ1DR               	(MCTL_PHY_BASE + 0x258)
#define P0_ZQ1SR               	(MCTL_PHY_BASE + 0x25C)
#define P0_ZQ2CR                (MCTL_PHY_BASE + 0x260)
#define P0_ZQ2PR               	(MCTL_PHY_BASE + 0x264)
#define P0_ZQ2DR               	(MCTL_PHY_BASE + 0x268)
#define P0_ZQ2SR               	(MCTL_PHY_BASE + 0x26C)
#define P0_ZQ3CR                (MCTL_PHY_BASE + 0x270)
#define P0_ZQ3PR               	(MCTL_PHY_BASE + 0x274)
#define P0_ZQ3DR               	(MCTL_PHY_BASE + 0x278)
#define P0_ZQ3SR               	(MCTL_PHY_BASE + 0x27C)
#define P0_DX0GCR0             	(MCTL_PHY_BASE + 0x280)
#define P0_DX0GCR1             	(MCTL_PHY_BASE + 0x284)
#define P0_DX0GCR2             	(MCTL_PHY_BASE + 0x288)
#define P0_DX0GCR3             	(MCTL_PHY_BASE + 0x28C)
#define P0_DX0GSR0             	(MCTL_PHY_BASE + 0x290)
#define P0_DX0GSR1             	(MCTL_PHY_BASE + 0x294)
#define P0_DX0GSR2             	(MCTL_PHY_BASE + 0x298)
#define P0_DX0BDLR0            	(MCTL_PHY_BASE + 0x29C)
#define P0_DX0BDLR1            	(MCTL_PHY_BASE + 0x2A0)
#define P0_DX0BDLR2            	(MCTL_PHY_BASE + 0x2A4)
#define P0_DX0BDLR3            	(MCTL_PHY_BASE + 0x2A8)
#define P0_DX0BDLR4            	(MCTL_PHY_BASE + 0x2AC)
#define P0_DX0BDLR5            	(MCTL_PHY_BASE + 0x2B0)
#define P0_DX0BDLR6            	(MCTL_PHY_BASE + 0x2B4)
#define P0_DX0LCDLR0           	(MCTL_PHY_BASE + 0x2B8)
#define P0_DX0LCDLR1           	(MCTL_PHY_BASE + 0x2BC)
#define P0_DX0LCDLR2           	(MCTL_PHY_BASE + 0x2C0)
#define P0_DX0MDLR             	(MCTL_PHY_BASE + 0x2C4)
#define P0_DX0GTR              	(MCTL_PHY_BASE + 0x2C8)
#define P0_DX1GCR0             	(MCTL_PHY_BASE + 0x300)
#define P0_DX1GCR1             	(MCTL_PHY_BASE + 0x304)
#define P0_DX1GCR2             	(MCTL_PHY_BASE + 0x308)
#define P0_DX1GCR3             	(MCTL_PHY_BASE + 0x30C)
#define P0_DX1GSR0             	(MCTL_PHY_BASE + 0x310)
#define P0_DX1GSR1             	(MCTL_PHY_BASE + 0x314)
#define P0_DX1GSR2             	(MCTL_PHY_BASE + 0x318)
#define P0_DX1BDLR0            	(MCTL_PHY_BASE + 0x31C)
#define P0_DX1BDLR1            	(MCTL_PHY_BASE + 0x320)
#define P0_DX1BDLR2            	(MCTL_PHY_BASE + 0x324)
#define P0_DX1BDLR3            	(MCTL_PHY_BASE + 0x328)
#define P0_DX1BDLR4            	(MCTL_PHY_BASE + 0x32C)
#define P0_DX1BDLR5            	(MCTL_PHY_BASE + 0x330)
#define P0_DX1BDLR6            	(MCTL_PHY_BASE + 0x334)
#define P0_DX1LCDLR0           	(MCTL_PHY_BASE + 0x338)
#define P0_DX1LCDLR1           	(MCTL_PHY_BASE + 0x33C)
#define P0_DX1LCDLR2           	(MCTL_PHY_BASE + 0x340)
#define P0_DX1MDLR             	(MCTL_PHY_BASE + 0x344)
#define P0_DX1GTR              	(MCTL_PHY_BASE + 0x348)
#define P0_DX2GCR0             	(MCTL_PHY_BASE + 0x380)
#define P0_DX2GCR1             	(MCTL_PHY_BASE + 0x384)
#define P0_DX2GCR2             	(MCTL_PHY_BASE + 0x388)
#define P0_DX2GCR3             	(MCTL_PHY_BASE + 0x38C)
#define P0_DX2GSR0             	(MCTL_PHY_BASE + 0x390)
#define P0_DX2GSR1             	(MCTL_PHY_BASE + 0x394)
#define P0_DX2GSR2             	(MCTL_PHY_BASE + 0x398)
#define P0_DX2BDLR0            	(MCTL_PHY_BASE + 0x39C)
#define P0_DX2BDLR1            	(MCTL_PHY_BASE + 0x3A0)
#define P0_DX2BDLR2            	(MCTL_PHY_BASE + 0x3A4)
#define P0_DX2BDLR3            	(MCTL_PHY_BASE + 0x3A8)
#define P0_DX2BDLR4            	(MCTL_PHY_BASE + 0x3AC)
#define P0_DX2BDLR5            	(MCTL_PHY_BASE + 0x3B0)
#define P0_DX2BDLR6            	(MCTL_PHY_BASE + 0x3B4)
#define P0_DX2LCDLR0           	(MCTL_PHY_BASE + 0x3B8)
#define P0_DX2LCDLR1           	(MCTL_PHY_BASE + 0x3BC)
#define P0_DX2LCDLR2           	(MCTL_PHY_BASE + 0x3C0)
#define P0_DX2MDLR             	(MCTL_PHY_BASE + 0x3C4)
#define P0_DX2GTR              	(MCTL_PHY_BASE + 0x3C8)
#define P0_DX3GCR0             	(MCTL_PHY_BASE + 0x400)
#define P0_DX3GCR1             	(MCTL_PHY_BASE + 0x404)
#define P0_DX3GCR2             	(MCTL_PHY_BASE + 0x408)
#define P0_DX3GCR3             	(MCTL_PHY_BASE + 0x40C)
#define P0_DX3GSR0             	(MCTL_PHY_BASE + 0x410)
#define P0_DX3GSR1             	(MCTL_PHY_BASE + 0x414)
#define P0_DX3GSR2             	(MCTL_PHY_BASE + 0x418)
#define P0_DX3BDLR0            	(MCTL_PHY_BASE + 0x41C)
#define P0_DX3BDLR1            	(MCTL_PHY_BASE + 0x420)
#define P0_DX3BDLR2            	(MCTL_PHY_BASE + 0x424)
#define P0_DX3BDLR3            	(MCTL_PHY_BASE + 0x428)
#define P0_DX3BDLR4            	(MCTL_PHY_BASE + 0x42C)
#define P0_DX3BDLR5            	(MCTL_PHY_BASE + 0x430)
#define P0_DX3BDLR6            	(MCTL_PHY_BASE + 0x434)
#define P0_DX3LCDLR0           	(MCTL_PHY_BASE + 0x438)
#define P0_DX3LCDLR1           	(MCTL_PHY_BASE + 0x43C)
#define P0_DX3LCDLR2           	(MCTL_PHY_BASE + 0x440)
#define P0_DX3MDLR             	(MCTL_PHY_BASE + 0x444)
#define P0_DX3GTR              	(MCTL_PHY_BASE + 0x448)

#define R_PRCM_BASE				(0x08001400)
#define VDD_SYS_PWROFF_GATING	(R_PRCM_BASE + 0x110)

#define CCM_PLL_BASE			(0x06000000)
#define CCM_PLL6_DDR_REG  		(CCM_PLL_BASE+0x014)

#define CCM_MOD_BASE		(0x06000400)
#define CCM_DRAMCLK_CFG_REG		(CCM_MOD_BASE+0x084)
#define CCM_AHB0_SOFT_RST_REG	(CCM_MOD_BASE+0x1a0)
#define CCM_AHB0_CLK_GAT_REG	(CCM_MOD_BASE+0x180)
#define CCM_PLL_LOCK_STA_REG	(CCM_PLL_BASE+0x09c)
/*
#define SDR_DFITCTRLUPDMIN	    (MCTL_CTL_BASE + 0x280)
#define SDR_DFITCTRLUPDMAX	    (MCTL_CTL_BASE + 0x284)
#define SDR_DFITCTRLUPDDLY	    (MCTL_CTL_BASE + 0x288)
#define SDR_DFIUPDCFG		    (MCTL_CTL_BASE + 0x290)
#define SDR_DFITREFMSKI		    (MCTL_CTL_BASE + 0x294)
#define SDR_DFITCRLUPDI		    (MCTL_CTL_BASE + 0x298)
#define SDR_DFITRCFG0		    (MCTL_CTL_BASE + 0x2ac)
#define SDR_DFITRSTAT0		    (MCTL_CTL_BASE + 0x2b0)
#define SDR_DFITRWRLVLEN	    (MCTL_CTL_BASE + 0x2b4)
#define SDR_DFITRRDLVLEN	    (MCTL_CTL_BASE + 0x2b8)
#define SDR_DFITRRDLVLGATEEN    (MCTL_CTL_BASE + 0x2bc)

#define SDR_DFISTCFG0		    (MCTL_CTL_BASE + 0x2c4)
#define SDR_DFISTCFG1		    (MCTL_CTL_BASE + 0x2c8)
#define SDR_DFITDRAMCLKEN	    (MCTL_CTL_BASE + 0x2d0)
#define SDR_DFITDRAMCLKDIS	    (MCTL_CTL_BASE + 0x2d4)
#define SDR_DFILPCFG0		    (MCTL_CTL_BASE + 0x2f0)

#define SDR_PIR					(MCTL_PHY_BASE + 0x04)
#define SDR_PGCR				(MCTL_PHY_BASE + 0x08)
#define SDR_PGSR				(MCTL_PHY_BASE + 0x0c)
#define SDR_DLLGCR				(MCTL_PHY_BASE + 0x10)
#define SDR_ACDLLCR				(MCTL_PHY_BASE + 0x14)
#define SDR_PTR0				(MCTL_PHY_BASE + 0x18)
#define SDR_PTR1				(MCTL_PHY_BASE + 0x1c)
#define SDR_PTR2				(MCTL_PHY_BASE + 0x20)
#define SDR_ACIOCR				(MCTL_PHY_BASE + 0x24)
#define SDR_DXCCR				(MCTL_PHY_BASE + 0x28)
#define SDR_DSGCR				(MCTL_PHY_BASE + 0x2c)
#define SDR_DCR					(MCTL_PHY_BASE + 0x30)
#define SDR_DTPR0				(MCTL_PHY_BASE + 0x34)
#define SDR_DTPR1				(MCTL_PHY_BASE + 0x38)
#define SDR_DTPR2				(MCTL_PHY_BASE + 0x3c)
#define SDR_MR0					(MCTL_PHY_BASE + 0x40)
#define SDR_MR1					(MCTL_PHY_BASE + 0x44)
#define SDR_MR2					(MCTL_PHY_BASE + 0x48)
#define SDR_MR3					(MCTL_PHY_BASE + 0x4c)
#define SDR_ODTCR				(MCTL_PHY_BASE + 0x50)
#define SDR_DTAR				(MCTL_PHY_BASE + 0x54)
#define SDR_DTDT0				(MCTL_PHY_BASE + 0x58)
#define SDR_DTDT1				(MCTL_PHY_BASE + 0x5c)
#define SDR_DCUAR				(MCTL_PHY_BASE + 0xc0)
#define SDR_DCUDR				(MCTL_PHY_BASE + 0xc4)
#define SDR_DCURR				(MCTL_PHY_BASE + 0xc8)
#define SDR_DCULR				(MCTL_PHY_BASE + 0xcc)
#define SDR_DCUGCR				(MCTL_PHY_BASE + 0xd0)
#define SDR_DCUTPR				(MCTL_PHY_BASE + 0xd4)
#define SDR_DCUSR0				(MCTL_PHY_BASE + 0xd8)
#define SDR_DCUSR1				(MCTL_PHY_BASE + 0xdc)
#define SDR_BISTRR				(MCTL_PHY_BASE + 0x100)
#define SDR_BISTMSKR0			(MCTL_PHY_BASE + 0x104)
#define SDR_BISTMSKR1			(MCTL_PHY_BASE + 0x108)
#define SDR_BISTWCR 			(MCTL_PHY_BASE + 0x10c)
#define SDR_BISTLSR 			(MCTL_PHY_BASE + 0x110)
#define SDR_BISTAR0 			(MCTL_PHY_BASE + 0x114)
#define SDR_BISTAR1 			(MCTL_PHY_BASE + 0x118)
#define SDR_BISTAR2 			(MCTL_PHY_BASE + 0x11c)
#define SDR_BISTUDPR 			(MCTL_PHY_BASE + 0x120)
#define SDR_BISTGSR 			(MCTL_PHY_BASE + 0x124)
#define SDR_BISTWER 			(MCTL_PHY_BASE + 0x128)
#define SDR_BISTBER0 			(MCTL_PHY_BASE + 0x12c)
#define SDR_BISTBER1 			(MCTL_PHY_BASE + 0x130)
#define SDR_BISTBER2 			(MCTL_PHY_BASE + 0x134)
#define SDR_BISTWCSR 			(MCTL_PHY_BASE + 0x138)
#define SDR_BISTFWR0 			(MCTL_PHY_BASE + 0x13c)
#define SDR_BISTFWR1 			(MCTL_PHY_BASE + 0x140)
#define SDR_ZQ0CR0	 			(MCTL_PHY_BASE + 0x180)
#define SDR_ZQ0CR1	 			(MCTL_PHY_BASE + 0x184)
#define SDR_ZQ0SR0	 			(MCTL_PHY_BASE + 0x188)
#define SDR_ZQ0SR1	 			(MCTL_PHY_BASE + 0x18c)
#define SDR_DX0GCR	 			(MCTL_PHY_BASE + 0x1c0)
#define SDR_DX0GSR0	 			(MCTL_PHY_BASE + 0x1c4)
#define SDR_DX0GSR1	 			(MCTL_PHY_BASE + 0x1c8)
#define SDR_DX0DLLCR 			(MCTL_PHY_BASE + 0x1cc)
#define SDR_DX0DQTR	 			(MCTL_PHY_BASE + 0x1d0)
#define SDR_DX0DQSTR 			(MCTL_PHY_BASE + 0x1d4)
#define SDR_DX1GCR	 			(MCTL_PHY_BASE + 0x200)
#define SDR_DX1GSR0	 			(MCTL_PHY_BASE + 0x204)
#define SDR_DX1GSR1	 			(MCTL_PHY_BASE + 0x208)
#define SDR_DX1DLLCR 			(MCTL_PHY_BASE + 0x20c)
#define SDR_DX1DQTR	 			(MCTL_PHY_BASE + 0x210)
#define SDR_DX1DQSTR 			(MCTL_PHY_BASE + 0x214)
#define SDR_DX2GCR	 			(MCTL_PHY_BASE + 0x240)
#define SDR_DX2GSR0	 			(MCTL_PHY_BASE + 0x244)
#define SDR_DX2GSR1	 			(MCTL_PHY_BASE + 0x248)
#define SDR_DX2DLLCR 			(MCTL_PHY_BASE + 0x24c)
#define SDR_DX2DQTR	 			(MCTL_PHY_BASE + 0x250)
#define SDR_DX2DQSTR 			(MCTL_PHY_BASE + 0x254)
#define SDR_DX3GCR	 			(MCTL_PHY_BASE + 0x280)
#define SDR_DX3GSR0	 			(MCTL_PHY_BASE + 0x284)
#define SDR_DX3GSR1	 			(MCTL_PHY_BASE + 0x288)
#define SDR_DX3DLLCR 			(MCTL_PHY_BASE + 0x28c)
#define SDR_DX3DQTR	 			(MCTL_PHY_BASE + 0x290)
#define SDR_DX3DQSTR 			(MCTL_PHY_BASE + 0x294)
*/
/*
#define CCU_PLL5CFG				(MCTL_CCU_BASE + 0x20)
#define CCU_AXIGATE				(MCTL_CCU_BASE + 0x5c)
#define CCU_AHBGATE0			(MCTL_CCU_BASE + 0x60)
#define CCU_AHBGATE1			(MCTL_CCU_BASE + 0x64)
#define CCU_MDFS_CLK			(MCTL_CCU_BASE + 0xf0)
#define CCU_MDFS_CFG			(MCTL_CCU_BASE + 0xf4)
#define CCU_AHB1_RST			(MCTL_CCU_BASE + 0x2c0)
*/
#define mctl_read_w(n)   		(*((volatile uint32 *)(n)))
#define mctl_write_w(n,c) 		(*((volatile uint32 *)(n)) = (c))

//for 1639 dram_init_driver
#define CCM_MOD_BASE			(0x06000400)
#define CCM_DRAMCLK_CFG_REG		(CCM_MOD_BASE+0x084)
#define AHB0_BUS				(1)
#define DRAM_CKID				((AHB0_BUS << 8) | 14)


#endif  //_MCTL_REG_H
